                              Release Notes
                              =============

                           Broadcom Bootcode Firmware 
                                    For 
                                  BCM5719                                  

                 Copyright (c) 2010-2016 Broadcom Corporation
                          All rights reserved.

-------------------------------
Version 1.51 - March 13, 2024   
-------------------------------

   Fixes:
   ======
   1.  Problem: DCSG01674700
       Need to restrict PCIe speed to Gen 1

       Cause:
       PCIe speed is restriced to Gen 1 for certain cards. That restriction
       is not present in existing bootcode.

       Fix:
       Restrict PCIe speed to Gen 1 for certain cards based on 4-part IDs.
       Populate SVID, SDID and Revision number in PCIe config space register
       during early part of bootcode initialization.


-------------------------------
Version 1.50 - September 29, 2023   
-------------------------------

   Fixes:
   ======
   1.  Problem: DCSG01557175
       BCM5719 GPIO2 workaround is not kicking in sometimes

       Cause:
       Checking PCIe status bit to decide on PERST trasitions
       doesn't seems to be reliable.

       Fix:
       Refine logic to determine PERST transitions so that GPIO2
       stays high during Vmain to Vaux transition.


Version 1.49 - September 8, 2023   
-------------------------------

   Enhancement:
   ============
   1. DCSG01545246: Add GPIO2 workaround for OEM 5719 4 port card to enable WoL
      in G3 state. 

-------------------------------
Version 1.48 - September 6, 2023   
-------------------------------

   Fixes:
   ======
   1.  Problem: DCSG01557175
       BCM5719 APE randomly fail to load NC-SI firmware

       Cause:
       Contention for NVRAM between RxCPU and APE firmware
       on powerup can cause APE firmware access to stop.

       Fix:
       Reset APE when RxCPU starts bootcode firmware.

-------------------------------
Version 1.47 - January 3, 2017   
-------------------------------

   Enhancement:
   ============                        
   1. CTRL-24102: Add OEM support for FoD option. 

-------------------------------
Version 1.46 - January 7, 2016   
-------------------------------

   Enhancement:
   ============                        
   1. Backed out the following change in last release (v1.45): 
      CTRL-20885: OEM enhancement request regarding PCIe link speed change for 
      Flow Control Initialization at Gen1.  Takeout 4 part id check.  Disable
      Gen1/Gen2 NVM user configuration.
             
-------------------------------
Version 1.45 - August 25, 2015   
-------------------------------

   Enhancement:
   ============                        
   1. CTRL-20885: OEM enhancement request regarding PCIe link speed change for 
      Flow Control Initialization at Gen1.  Takeout 4 part id check.  Disable
      Gen1/Gen2 NVM user configuration.
             
-------------------------------
Version 1.44 - August 11, 2015   
-------------------------------

   Enhancement:
   ============                        
   1. CTRL-20885: OEM enhancement request regarding PCIe link speed change for 
      Flow Control Initialization at Gen1.
                   
-------------------------------
Version 1.43 - June 4, 2015   
-------------------------------

   Fixes:
   ======
   1.  Problem: CASE#923947
       The SPI clock (i.e. SCLK) runs twice speed 
       faster than the default on some OEM platforms.

       Cause:
       The function, which handles the VPD event, 
       accidentally clears the register offset 0x7014 
       Bit [7] that changes SPI_CLK_DIV.

       Fix:
       Fixed the function in question and resolved the issue.
                          
-------------------------------
Version 1.42 - April 8, 2015   
-------------------------------

   Enhancement:
   ============		                         
   1. (JIRA) (CTRL-20518) 909424: Bootcode version update

-------------------------------
Version 1.41 - November 19, 2014   
-------------------------------

   Fixes:
   ======
   1. Problem: CQ74011
      Share memory offsets overwritten due to a change in a 
      common header file between bootcode and PM Offload firmware.

      Cause:
      Changes made to this common header intended for PM offload 
      firmware inadvertently overwrites certain offset in share 
      memory for bootcodes compiled with this header file.
     
      Fix:
      fix affected header file and re-release all affected bootcodes.
    
-------------------------------
Version 1.40 - October 22, 2014   
-------------------------------

   Enhancement:
   ============		                         
   1. Undo CQ73916. Force PCIE Link to Gen 1 for specific OEM.
    
-------------------------------
Version 1.39 - October 21, 2014   
-------------------------------

   Enhancement:
   ============		                         
   1. CQ73784.  NX1 NVRAM L0s & L1s NVRAM entries to match NX2 designs.
      Two NVRAM bits are defined to control ASPM support.

   2. CQ73916. Force PCIE Link to Gen 1 for specific OEM.
    
-------------------------------
Version 1.38 - December 20, 2013   
-------------------------------
   Enhancement:
   ============
   1. CQ72062: OEM specific enhancement request to address PCIe link 
      training issue due to improper receiver termination at the link 
      partner.

-------------------------------
Version 1.37 - November 1, 2013   
-------------------------------
   Fixes:
   ======
   1. Problem: CQ71689
      Device many report "no firmware running" when Inbox driver is used.

      Cause:
      Due to the lower core clock speed, the driver may have missed the
      signature deposited by the BootCode.  As a result, the driver may 
      report "no firmware running".
     
      Fix:
      Bootcode will force the core clock to the highest speed at the 
      beginning and undo forcing before entering the service loop.
	  The signature will then be deposited in a earlier time which will
      avoid this issue to happen.
	  
   Enhancement:
   ============
   1. Enhanced CQ 56037. Make port flapping avoidance feature available for 
      all systems.
	  
-------------------------------
Version 1.36 - October 11, 2013
-------------------------------  
   Enhancement:
   ============		
   1. CQ71212: Adding a NVRAM Control bit (offset 0x21C[1]) to enable/disable 
      AutoNeg 1G half duplex advertisement.
	  
   2. CQ71164: Enabled Feature on Demand for specific systems.
	  
-----------------------------
Version 1.35 - August 9, 2013
-----------------------------    
   Enhancement:
   ============		
   1. CQ69831: OEM enhancement request regarding PCIe link speed change for 
      Flow Control Initialization at Gen1.
    
-----------------------------
Version 1.34 - March 26, 2013
-----------------------------    
   Enhancement:
   ============		
   1. CQ67974 - Add NVM-CFG option to disable *L1 re-entry* while in D3H.
      A new NVM-CFG bit has been defined at offset 0x21C[0] to disable
      *L1 re-entry*. NVRAM offset 0x21C will be copied to shared memory
      offset 0xe0C.
    
   2. CQ68083 - To support Feature on Demand, Bootcode will disable the ports
      only when driver is absent.  That means if Reset Magic is not in shared
      memory offset 0xb50, Bootcode will disable the ports.  
	  
-------------------------------
Version 1.33 - January 23, 2013
-------------------------------    
   Fixes:
   ======
   1. Problem: CQ67387
      PCIe Gen2 (-3.5dB) Tx Template failure

      Cause:
      The default PCIe Gen2 Transmitter amplitude is not preserved. Bootcode
      overwrites the PCIe Gen2 Transmitter amplitude when programming PCIe Tx
      De-Emphasis.
     
      Fix:
      Bootcode will preserve the PCIe Gen2 Transmitter amplitude to resolve
      this issue.

   2. Problem: CQ67388
      PCIe Tx de-emphasis for Gen2

      Cause:
      In b57diag secfg #68 configuration controls the PCIe Tx de-empahsis for
      both Gen1 and Gen2. It's suggested to differentiate this option between
      Gen1 and Gen2 for better clarification.
     
      Fix:
      Using the existing defined control bits to control the PCIe Tx
      de-empahsis for Gen1. Defined two more control bits in NVRAM to control
      the PCIe Tx de-empahsis for Gen2. The default setting is -3.5dB for Gen1
      and -6 dB for Gen2.
      
   Enhancement:
   ============		
   1. Preserve the configuration data in shared memory in Phase 2 Bootcode
      since Bootcode can no longer be able to read these data after driver
      enabled Interesting packet WOL (0x400[19] = 1).

--------------------------------
Version 1.32 -  October 18, 2012
--------------------------------    
   Enhancement:
   ============		
   1. Enabled CPMU power saving modes in Phase 2 instead of Phase 1 to reduce
      Bootcode loading time.
       
   2. Added Feature on Demand.  
      Two new configuration bits in NVRAM are defined per device to select the
      number of ports that needed to be enabled. Defined one new configuration
      bit per port to identify whether the port is support FoD capable.
   
----------------------------
Version 1.31 - June 20, 2012
----------------------------    
   Enhancement:
   ============		
   1. Add TPH feature support.
      Defined to NVRAM control bits to control TPH feature.
       00: Disable 
       01: Advertise TPH without ST Mode
       10: Advertise TPH with ST Mode 
       
   2. Copy the 4 part ID from Reg 0x6434 and Reg 0x6438 to APE shared memory
      rxCPU write segment area.
 
   3. Minimizing the NVRAM access in Phase 2 Bootcode.
   
-----------------------------
Version 1.30 - April 24, 2012
-----------------------------

   Fixes:
   ======
   1. Problem: CQ62817
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not take effect.
	  
      Cause:
      NVRAM secfg #68 PCIe Tx De-Emphasis option does not support PCIe Gen 2.

      Change:
      Added PCIe Gen 2 Tx De-Emphasis support.
      
-----------------------------
Version 1.29 - March 07, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode will copy func_mode information to RxCPU and APE Shared Memory
      for drivers and APE FW after the device is out from reset and when
      Vmain is present.
       
-----------------------------
Version 1.28 - March 05, 2012 
-----------------------------    

   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW after the device is out from reset.  Bootcode will
      poll pcie register 0x408 bit 7 for first config done to determine
      whether the device is out from reset.
  
   2. In setting up PCIe Tx De-emphasis, the Bootcode will read back the
      serdes register to make sure the register is updated as expected. 
      
--------------------------------
Version 1.27 - February 16, 2012 
--------------------------------                 

   Enhancements:
   =============
   1. Change the Boot code to setup both MSIX table offset and PBA table
      offset to page aligned.
   
--------------------------------
Version 1.26 - December 28, 2011 
--------------------------------

   Fixes:
   ======
   1. Problem: 
      The LED remains on after DOS ungraceful shutdown when WOL is disabled. 
	  
      Cause:
      The root cause is that Bootcode cannot successfully power down the
      unused GPHY. Bootcode powered down unused GPHY by read/modify/write mii
      reg 0x00 to set GMII_CONTROL_ISOLATE bit and GMII_CONTROL_POWER_DOWN
      bit. When Bootcode write back to mii reg 0x0, the
      MII_CONTROL_AUTONEG_ENA bit is still set which keeps the GPHY LED
      remain on.

      Change:
      Modified Bootcode not to read/modify/write when updating mii reg 0x00.
      Bootcode will only write GMII_CONTROL_ISOLATE bit and
      GMII_CONTROL_POWER_DOWN bit to mii reg 0x00 to completely power down the
      unused GPHY.
	  
--------------------------------
Version 1.25 - November 15, 2011 
--------------------------------

   Enhancements:
   =============
   1. Provide the access to Network SerDes adjustment parameter.
      Defined 4 control bits to adjust Network SerDes TX Amplitude and 
      Pre-emphasis. Set the default NVRAM settings for the Network SerDes TX             
      Amplitude and Pre-emphasis to be closer to the HW default as possible. 
      The fiber mode output voltage measurements are closest to the HW default
      when the TxAmpl/TxPre configuration is 01/00. This common default
      applies to both fiber and SGMII modes.
	  
   2. Removed V1.22 changes.
      BC set BIT 12 and BIT 11 of Reg 0x40C to 11b in LINK/ACTIVITY LED Mode
      and SPEED10/100 LED Mode.
	  
---------------------------------
Version 1.24 - September 21, 2011 
---------------------------------

   Fixes:
   ======
   1. Problem: 
      Get version ID command in NCSI FW does not return correct IDs. 

      Cause:
      BC copy the svid and ssid to the APE shared memory. The get version ID 
      command in NCSI FW will read the IDs from here. Each port has its own
      svid and ssid stored in the NVRAM and each port has its own space in APE
      shared memory to store these IDs. However BC only copy the svid and ssid
      of port0 from NVRAM offset to the APE shared memory for all ports. 
      
      Change:
      BC will copy the port svid and ssid to its own space of the APE shared
      memory.

------------------------------
Version 1.23 - August 31, 2011 
------------------------------

   Enhancements:
   =============
   1. Removed CQ58029 implementation.
   
------------------------------
Version 1.22 - August 26, 2011 
------------------------------

   Fixes:
   ======
   1. Problem: 
      BC set BIT 12:11 of Reg 0x40C in LINK/ACTIVITY LED Mode and SPEED10/100
      LED Mode.

      Change:
      Follow the Register spec to set BIT 12:11 to 00 in both modes.

   Enhancements:
   =============
   1. Modifiy CQ58029 implementation. 
   
-------------------------------
Version 1.21 -  August 22, 2011 
-------------------------------
   Enhancements:
   =============
   1.CQ58029:  Prevent Entry into PCIe compliance mode.	
   
----------------------------
Version 1.20 - July 22, 2011 
----------------------------

   Fixes:
   ======
   1. Problem: 
      In Func_mode support, BC may run into a infinite loop when detecting
      whether the device has come out from reset if the device states in
      reset.

      Change:
      Modify BC to poll for a finite number of times to avoid a dead lock
      situation.
	  
----------------------------
Version 1.19 - July 12, 2011   
----------------------------
   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW.  A signature (0x362c) has been introduced for the
      func_mode information validation.  Driver and APE FW should validate the
      func_mode information in the shared memory by checking this signature.
	  
----------------------------
Version 1.18 - July 06, 2011   
----------------------------
   Enhancement:
   ============		
   1. Bootcode copy func_mode information to RxCPU and APE Shared Memory for
      drivers and APE FW.
	  
----------------------------
Version 1.17 - June 21, 2011   
----------------------------
   Enhancement:
   ============
   1. Modified OS absent mode EEE script to improve the link stability.
      (17[8:0] = 1FF)
 
   2. Set the Mac Core Clock in Link Aware Clock Policy register to 6.25MHz. 
   
   3. CQ56461: OEM enhancement request regarding preservation of link speed
      and status
	  
----------------------------
Version 1.16 - June 09, 2011   
----------------------------
   Enhancement:
   ============
   1. Modified Bootcode to continue monitoring the link status after entering
      Vaux only mode.
 
   2. Addressed CQ 56037 to preserve the link speed and link status during 
      system reset or ungraceful shutdown when the driver is absent and port
      flapping avoidance feature is enabled.
	  
---------------------------
Version 1.15 - May 09, 2011   
---------------------------

   Enhancement:
   ============
   1. Update OS absent mode EEE script. The OS absent mode EEE support is
      disabled by default in NVRAM.
	      
-----------------------------
Version 1.14 - April 15, 2011   
-----------------------------

   Enhancement:
   ============
   1. CQ 54515: Disable EEE by default in Boot Code. Set the default state of
      the EEE_Enable bit in NVRAM to disable.
	  
-----------------------------
Version 1.13 - March 28, 2011   
-----------------------------

   Enhancement:
   ============
   1. Adding Single Bit ECC Error Correction support.
      Defined Bit 2 of Extended Configuration in NVRAM to control 
      whether the chip will generate GRC reset upon detection of ECC error.  
	  
   2. Adding CL73 support.  BC will detect whether CL73 is enabled by 
      hardware strapping.  If it is enabled, BC will perform CL73 setup.
	  
-----------------------------
Version 1.12 - March 18, 2011   
-----------------------------
	  
   Enhancement:
   ============
   1. Adding Extended VPD block support.
	  
--------------------------------
Version 1.11 - February 25, 2011   
--------------------------------
	  
   Enhancement:
   ============
   1. Reducing the link status polling frequency to every 1s when EEE is
      enabled.
   2. Modify Force Expansion ROM Advertisement Configuration support.
      Bootcode  will not set bit 16 of Shared Memory 0xb58 when Force
      Expansion ROM Advertisement Configuration is enabled.  This bit will
      only be set when PXE enable bit is set in NVRAM.
	  
--------------------------------
Version 1.10 - February 17, 2011   
--------------------------------
	  
   Enhancement:
   ============
   1. CQ 53107 - Force Expansion ROM Advertisement Configuration.
      Defined Extended Configuration for each port started at NVRAM offset
      0x278. BIT_1 of Extended Configuration is defined as Force Expansion 
      ROM Advertisement Enable. BC will enable/disable Expansion ROM
      Advertisement based on the state of the Force Expansion ROM
      Advertisement Enable bit after reset. BC will copy Extended
      Configuration to RxCPU Shared Memory offset 0xdf8 and APE RxCPU Shared
      Memory.
   
--------------------------------
Version 1.09 - February 14, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: 
      BC does not enable EEE at 100M.

      Cause:
      EEE enable logic fails to enable EEE at 100M.
      
      Change:
      Modify the EEE enable logic to resolve the issue.
	  
--------------------------------
Version 1.08 - February 11, 2011   
--------------------------------

   Fixes:
   ======
   1. Problem: 
      BC enabled LPI with non-EEE link partner.

      Cause:
      There is an issue in the original EEE enable script. One of the checking
      conditions in this EEE enable script will fall through even with link
      partner is not supporting EEE. As a result the BC will enable LPI even
      with non-EEE link partners.
      
      Change:
      Modify the EEE enable logic in the script to resolve the issue.
	  
   Enhancement:
   ============
   1. Enabled Link Idle Mode.
   
-------------------------------
Version 1.07 - January 06, 2011   
-------------------------------

   Fixes:
   ======
   1. Problem: CQ52007
      New EEE configuration in NVRAM for BC for Cotopaxi

      Change:
      Using Bit 13 of HW_CONFIG instead of Bit 27 of Feature_Config to
      enable/disable EEE. B57diag V14.23 or later will support this change. 
	  
   2. Problem: 
      Bootcode will program port 0 with port 1 SDID.

      Cause:
      In Dual SDID per port support, there is a bug in the SDID select logic
      in Bootcode.
	  
      Change:
      Fixed the logic in question to resolve the issue.
	  
   Enhancements:
   =============
   1. Copy HW_CONFIG to APE shared memory.
   
   2. Moved up the Gen1/Gen2 selection logic to give BC more time to program
      the selection.
   
---------------------------------
 Version 1.06 - December 15, 2010 
---------------------------------
   Enhancement:
   ============
   1. Adding NVRAM control bit to Select Gen1/Gen2.
	  
   2. Adding Dual SDID per port support.  Dual SDID per port will be stored in
      NVRAM starting from 0x22C.
	  
   3. BC will drive GPIO2 to low to avoid power glitch during Vaux to Vmain
      transition.

   4. BC will copy feature_config from RxCPU shared memory to APE shared
      memory after reset.
	  
   5. Added APE Heartbeat Monitoring function to monitor the heartbeat of APE.  
      In case the heartbeat is not updating for a few cycles, Bootcode will 
      reset APE. Before APE reset, bootcode will update RxCPU_RESET_APE_COUNT 
      and copy APE_STATE register to RxCPU_LAST_APE_STAT and 
      APE_SHMEM_APE_FW_STATUS_ADDR to APE_SHMEM_RXCPU_LAST_APE_FW_STAT in APE 
      shared memory. The APE Heartbeat Monitoring function will be disabled if 
      the APE heartbeat interval at offset 0x24 in APE shared memory is zero.
      In addition, the monitoring period will be defaulted to 6.2 sec if the 
      APE heartbeat interval is too short.  This function is enabled or
      disabled by Bit_0 of APE_FW_BEHAVIOR.  
  						  
--------------------------------
 Version 1.05 - December 2, 2010 
--------------------------------
   Enhancement:
   ============
   1. Adding NVRAM control bit to control enabling and disabling EEE support
      in OS absent mode. The default setting is enable.
	  
   2. Updating the Virtual Mac Support. Bootcode will use the Virtual Mac
      Address if Virtual Mac is enabled. Otherwise, Mac Address will be taken
      from NVRAM.
	  
   3. Adding NVRAM control bit to control PCIe Tx De-emphasis Configuration.  
	  
   4. Adding NVRAM control bit to control enabling and disabling of NCSI
      Clock Output Disable.
  
	  
---------------------------------
 Version 1.04 - November 12, 2010 
---------------------------------

   Fixes:
   ======
   1. Problem: 
      BC locked up the MII Mutex.
	  
      Cause:
      Bootcode did not release MII Mutex during EEE setup.

      Change:
      Bootcode will release MII Mutex after accessing MII Reg.  
						  
--------------------------------
 Version 1.03 - November 1, 2010 
--------------------------------

   Fixes:
   ======
   1. Problem: 
      There is an issue in Cotopaxi whereby internal 
      TLP clock derived from PCie Serdes is not available 
      when PERST# is low and this will not allow us to do 
      magic packet wakeup for OOB WOL case.

      Change:
      Workaround for this would be to derive TLP clock from 
      internal PLL (always running and by setting x3638 bit[26] =1) 
      when system is running on VAUX and then switch to PCie 
      Serdes source during normal operation (clearing x3638 bit[26] = 0).  

   Enhancement:
   ============
   1. Adding EEE support in OS absent mode.

   2. Using Phy register 0x00 bit 11 to power down the 
      Serdes port instead of Reg 0x3638 bit 15.
      Reg 0x3638 bit 15 will power down all Serdes ports.  


--------------------------------
 Version 1.02 - October 27, 2010 
--------------------------------

   Enhancement:
   ============
   1. Using Phy register 0x00 bit 11 to power down the GPHY instead of
      Reg 0x3638 bit 0. Reg 0x3638 bit 0 will power down all GPHY ports.  

--------------------------------
 Version 1.01 - October 21, 2010 
--------------------------------

   Enhancement:
   ============
   1. Set TLP Clock Source to 125Mhz from NCSI PLL.

--------------------------------
 Version 1.00 - October 20, 2010 
--------------------------------

   Enhancement:
   ============
   1. Adding APE support.

   2. Enabled using APE Mutex.  Older BC images did not use APE Mutex
      to prevent hanging the BC when running with APE absent FPGA images.

   3. Speed up NVRAM clock when accessing VPD data.

----------------------------------
 Version 0.08g - September 1, 2010 
----------------------------------

   Fixes:
   ======
   1. Problem: 
      Device Class Code is erased by BC.
 
      Cause:
      When updating the ASIC Revision at PCI-E Reg 0x8, BC unexpectedly 
      erased the Device Class Code at Reg 0x9.  
      
      Change:
      BC will preserve the Device Class Code at Reg 0x9 when updating
      the ASIC Revision at PCI-E Reg 0x8.

--------------------------------
 Version 0.07g - August 31, 2010  
--------------------------------

   Fixes:
   ======
   1. Problem: CQ48144
      5718 unable wake up when WOL is only enabled in Driver.
 
      Cause:
      When driver enable WOL on only one port and the WOL Enable bits are not
      set in NVROM of both ports,  the Bootcode of the WOL disabled 
      port will power down the device since it does not aware of WOL is
      enabled on the other port. 
      
      Change:
      BC of the WOL disabled port will HALT RxCPU and power down the 
      GPHY instead of IDDQ the device on the way down.  

   Enhancement:
   ============
   1. Program x4910 bits[19:16] = 4'b1111to set the RDMA non-lso, BD request
      size to 4K to improve performance.


--------------------------------------------
 Version 0.06g (a.k.a 0.96g) - June 22, 2010  
--------------------------------------------
 
   Fixes:
   ======
   1. Problem (CQ48435): 
      [Cotopaxi FPGA]:NVRAM corruption when system power cycle 
      with WOL disabled in bootcode.
 
      Cause:
      The issue is due to bootcode accessing the NVRAM when 
      the NVRAM interface is still in reset state or doing NVRAM detection.
      When Fastboot is enabled, bootcode will access the NVRAM right away
      after reset while the NVRAM interface may not be ready. It may result
      in NVRAM corruption.  The corrupted data may then be used as device id
      and vendor id which cause device cannot be detected by B57diag.  

      Change:
      Bootcode will wait until the NVRAM interface is ready before accessing 
      the NVRAM to prevent NVRAM data corruption.

      
-----------------------------
 Version 0.05g - May 11, 2010 
-----------------------------
 
   Enhancement:
   ============
   1. Adding Function Mode support.  Bootcode will enable and disable port
      based on func_mode[4:0] input pins which are controlled by system BIOS.
      Bootcode will evaluate them after the device comes out of system reset 
      (PERST_L) and perform necessary tasks to safely power down disabled 
      functions. 

   2. Bootcode will power down the GPHY/SGMII port if WOL and NCSI are
      disabled on the target port. Bootcode will IDDQ the device if WOL and
      NCSI are disabled in all ports.

-----------------------------
 Version 0.04g - May 03, 2010 
-----------------------------
 
   Enhancement:
   ============
   1. Only allow Function 0 bootcode to enable/disable the switching
      regulator.

   2. Initializing and enabling ECC protection against data corruption in
      RxMbuf, TxMbuf and BD SRAM.

-------------------------------
 Version 0.03g - April 28, 2010 
-------------------------------
 
   Fixes:
   ======
   1. Problem (CQ47332): 
      [Cotopaxi FPGA]:MAC address became "00:00:00:00:00:00" in 2K3.
 
      Cause:
      Bootcode did not update the Mac Address in the RxCpu Shared 
      Memory space.  
 
      Change:
      Updating the Mac Address in the RxCpu Shared Memory space
      resolved the issue.

-------------------------------
 Version 0.02g - April 23, 2010 
-------------------------------
   Enhancement:
   ============
   1. This bootcode controls the Time Sync GPIO Mapping 
      and the Switching Regulator Power Down base on the 
      new definition of the NVRAM configuration bits.  
      Bit 18:19 of NVRAM offset 0xC8, 0xD8, 0x254 and 0x264
      are used to control the Time Sync GPIO Mapping for each port.  
      Bit 7 of NVRAM offset 0xBC is used to control the Switching
      Regulator Power Down. 

   2. Adding a new NVRAM Configuration bit for each port
      to enable and disable the Time Sync Mode.  Bit 17 
      of offset 0xC8, 0xD8, 0x254, and 0x264 are used to control 
      Time Sync Mode for each port.

-------------------------------
 Version 0.01g - April 22, 2010 
-------------------------------
   Note:
   ======
   1. Initial engineering release
      This release is for 5719 emulation.

   2. This bootcode does not use APE Mutex Registers. 




